/** \file sja1000.h * * SJA1000 CAN driver for Linux 2.4.x * PeliCAN mode is supported * * Existing modes for the Parallel port are: * SPP: Standard parallel port, 150Kb/s, unidirectional * EPP: Enhanced parallel port, 2Mb/s, bidirectional * ECP: Standard Capabilities port, ?, bidirectional DMA channel * * * \author Cristiano Brudna, 2001, 2002, 2003 * \author Hubert Piontek, 2003 * * \date 2001, 2002, 2003 * * University of Ulm, Germany */ #include #include typedef u_int32_t CanId; /* struct to hold a single can message */ typedef struct { CanId id; int type; /* standard or extended frame */ int rtr; /* remote transmission */ int len; /* data length 0..8 */ unsigned char d[8]; /* data bytes */ struct timeval timestamp; /* timestamp */ } canmsg; /* will hold the two bytes defining the can bus timing */ typedef struct { unsigned char bt0; unsigned char bt1; } canconfig; /* Parallel port */ #define BASE_ADDR 0xf4A00000 /* taken from the BIOS setup */ #define DEF_BA_STR "0xf4A00000" #define IRQ LUBBOCK_IRQ(2) /* taken from the BIOS setup */ #define DEF_IRQ_STR "LUBBOCK_IRQ(2)" /* # of ports to allocate */ #define NUMBER_OF_PORTS 8 /* port definitions relative to the base address */ #define PP_DATA (port+0) #define PP_STATUS (port+1) #define PP_CONTROL (port+2) #define EPP_ADDR (port+3) #define EPP_DATA (port+4) /* Definitions of SPP Control Bits */ #define SPP_ENABLE_BIDIR_MODE 0x20 #define SPP_ENABLE_IRQ_VIA_ACK 0x10 #define SPP_SELECT_PRINTER 0x08 #define SPP_INITIALIZE_PRINTER 0x04 #define SPP_AUTO_LINEFEED 0x02 #define SPP_STROBE 0x01 /* Definitions of SPP Status Bits */ #define SPP_BUSY 0x80 #define SPP_ACK 0x40 #define SPP_PAPER_OUT 0x20 #define SPP_SELECT_IN 0x10 #define SPP_ERROR 0x08 #define SPP_IRQ 0x04 /* highest accessible register no. on SJA1000 */ #define MAX_REG_NO 0x1F // Taken from donglreg.c from phytec: // // Manche Port-C-Leitungen werden zusaetzlich invertiert, // daher muessen Ausgaben nach Port C immer mit einem "XOR 0x0B" // verrechnet werden. // --> Some bits of the control port are being inverted in hardware, some others are not. // Therefore, do XOR 0x0B on what you want to write to the port, and you're all set. // The following #define does that for you. #define WR_PP_CONTROL( x ) outb( (x) ^ 0x0B, PP_CONTROL ) // The next #define allows you to write the register address and combine it with the read/write flag for // the current access cycle to the SJA1000. It has two parameters, the first one is the register number, // the second is the read/write flag. #define WR_REGISTER( x, y ) outb( ((x) & MAX_REG_NO) | ((y) << 2), PP_DATA ) // (y) << 2 macht aus den 0x20 fuer DONGLE_READ_CYCLE die benoetigten 0x80 fuer das r/w Bit im CPLD-Register ;) // read/write flags for WR_REGISTER and WR_PP_CONTROL #define DONGLE_WRITE_CYCLE 0x00 #define DONGLE_READ_CYCLE 0x20 // #defines for the CPLD control lines (mapped to the control register of the parallel port) #define DONGLE_UPPER_NIBBLE SPP_ENABLE_IRQ_VIA_ACK #define DONGLE_ispEN SPP_SELECT_PRINTER #define DONGLE_x SPP_INITIALIZE_PRINTER #define DONGLE_Mode SPP_AUTO_LINEFEED #define DONGLE_Strb SPP_STROBE // DONGLE_STANDARD is a #define for the standard values of the control lines for the dongle #define DONGLE_STANDARD (DONGLE_UPPER_NIBBLE | DONGLE_ispEN | DONGLE_x | DONGLE_Mode | DONGLE_Strb) // DONGLE_WRITE_ADDRESS is a #define used to tell the dongle to read an address #define DONGLE_WRITE_ADDRESS (DONGLE_UPPER_NIBBLE | DONGLE_ispEN | DONGLE_x | DONGLE_Mode) /* Standard operation mode to the (MODE register) FIXME SJA1000 ??? */ #define STANDARD_MODE 0x08 /* Operations of the COMMAND register FIXME SJA1000 ??? */ #define TRANSMISSION_REQUEST 0x01 #define ABORT_TRANSMISSION 0x02 #define RELEASE_RECEIVE_BUFFER 0X04 #define CLEAR_DATA_OVERRUN 0x08 #define SLEEP 0x10 /* State of the controller FIXME SJA1000 ??? */ #define ACTIVE 0 #define PASSIVE 1 /* Operations of the ioctl() comand of the driver */ #define CAN_MAJOR 120 #define CAN_IOC_MAGIC 'k' #define CAN_IOCSBAUD _IOW(CAN_IOC_MAGIC, 1, 8) /* set baud rate */ #define CAN_IOCSAMASK _IOW(CAN_IOC_MAGIC, 2, 8) /* set acceptance mask */ #define CAN_IOCSACODE _IOW(CAN_IOC_MAGIC, 3, 8) /* set acceptance code */ #define CAN_IOCCRBUF _IOW(CAN_IOC_MAGIC, 4, 8) /* clear read buffer */ #define CAN_IOCCWBUF _IOW(CAN_IOC_MAGIC, 5, 8) /* clear write buffer */ #define CAN_IOCRREG _IOR(CAN_IOC_MAGIC, 6, 8) /* read register */ #define CAN_IOCRTTS _IOR(CAN_IOC_MAGIC, 7, 8) /* read last transmit timestamp */ #define CAN_IOCSACTIVE _IOW(CAN_IOC_MAGIC, 8, 8) /* set active mode */ #define CAN_IOCSPASSIVE _IOW(CAN_IOC_MAGIC, 9, 8) /* set passive mode */ #define CAN_IOCRAPS _IOR(CAN_IOC_MAGIC, 10, 8) /* read active/passive status */ #define CAN_IOCSBTR _IOW(CAN_IOC_MAGIC, 11, 8) /* set bit timing registers 0 and 1 */ // FIXME what's this for? max. ioctl code no? #define CAN_IOC_MAXNR 11 /* Types of can frames */ #define STANDARD 0 #define EXTENDED 1 /* Definition of possible baudrates for the Can-Bus */ /* Using defines for ease of reading */ #define B1000 0 /* 1 MBit/s */ #define B500 1 /* 500 Kbit/s */ #define B250 2 /* 250 Kbit/s */ #define B125 3 /* 125 Kbit/s */ #define B20 4 /* 20 Kbit/s */ /* size of the read/write buffers, in terms of canmsg structs */ #define BUFFER_SIZE 150 #define MSG_LENGTH sizeof(canmsg) // FIXME WTF? #define RB_FULL_COUNTER_LIMIT 20 typedef struct CAN_Dev { int baud_rate; /* baud rate of the bus */ int frame_mode; /* normal (0) or extended (1) mode */ int active_passive_status; /* current state of the controller */ int count; /* user application counter */ int rb_full_counter; /* read_buffer full counter (protection against too many interrupts FIXME wtf? */ canmsg read_buf[BUFFER_SIZE]; int nm_rb; /* number of messages in the read buffer */ int rp_rb; /* read position of the read buffer */ int wp_rb; /* write position of the read buffer */ canmsg write_buf[BUFFER_SIZE]; int nm_wb; /* number of messages in the write buffer */ int wp_wb; /* write position of the write buffer */ int rp_wb; /* read position of the write buffer */ }CAN_Dev; typedef struct { int baudnr; unsigned char bt0; unsigned char bt1; }bus_param; /* * List of registers of the SJA1000, as defined in the datasheet on pages 21, 22 * The list is composed of the registers in the PeliCAN mode of the SJA1000. * Some of these registers only apply to the RESET MODE; DATA and IDENTIFIER, however, * do not apply to the RESET MODE, and are valid only for EXTENDED CAN FRAMES. * There is not only one DATA register, but DATA is the first of the eight consecutive * registers holding the can data. With the IDENTIFIER register, similar things apply --- see datasheet ;) * * A write access to register address 31 will generate a hardware reset of the SJA1000 for the * CAN dongle. This is done by the CPLD inside the dongle. */ #define CAN_MODE 0 #define CAN_COMMAND 1 #define CAN_STATUS 2 #define CAN_INTERRUPT 3 #define CAN_INTERRUPT_ENABLE 4 #define CAN_BUS_TIMING_0 6 #define CAN_BUS_TIMING_1 7 #define CAN_OUTPUT_CONTROL 8 #define CAN_TEST 9 #define CAN_ARBITRATION_LOST_CAPTURE 11 #define CAN_ERROR_CODE_CAPTURE 12 #define CAN_ERROR_WARNING_LIMIT 13 #define CAN_RX_ERROR_COUNTER 14 #define CAN_TX_ERROR_COUNTER 15 #define CAN_FRAME_INFORMATION 16 #define CAN_IDENTIFIER 17 #define CAN_ACCEPTANCE_MASK 20 #define CAN_DATA 21 #define CAN_RX_MESSAGE_COUNTER 29 #define CAN_CLOCK_DIVIDER 31 #define CAN_INTERNAL_RAM 32