#define SPRT0_BDV	   0xff88	/* serial port bauddiv reg  */
#define SPRT0_RX	   0xff86	/* serial port receive reg  */
#define SPRT0_TX	   0xff84	/* serial port transmit reg */
#define SPRT0_STAT	   0xff82	/* serial port status reg   */
#define SPRT0_CTL	   0xff80	/* serial port control reg  */

#define SPRT1_BDV	   0xff18	/* serial port bauddiv reg  */
#define SPRT1_RX	   0xff16	/* serial port receive reg  */
#define SPRT1_TX	   0xff14	/* serial port transmit reg */
#define SPRT1_STAT	   0xff12	/* serial port status reg   */
#define SPRT1_CTL	   0xff10	/* serial port control reg  */

/*
// Asynchronous serial port status register (SPRT_STAT) ES only
*/

#define SPRT_STAT_BRK1_ES     0x0400	/*  Long break detected    */
#define SPRT_STAT_BRK0_ES     0x0200	/*  Short break detected   */
#define SPRT_STAT_RB8_ES      0x0100	/*  Receive data bit 9	   */
#define SPRT_STAT_RDR_ES      0x0080	/*  Receive data ready	   */
#define SPRT_STAT_THRE_ES     0x0040	/*  Tx holding reg. empty  */
#define SPRT_STAT_FRAME_ES    0x0020	/*  Framing error detected */
#define SPRT_STAT_OVERFLOW_ES 0x0010	/*  Overrun error detected */
#define SPRT_STAT_PARITY_ES   0x0008	/*  Parity error detected  */
#define SPRT_STAT_TEMT_ES     0x0004	/*  transmitter is empty   */
#define SPRT_STAT_HS0_ES      0x0002	/*  *CTS signal asserted   */

/*
//  all Sbreaks must set this bit
*/
#define SPRT_STAT_BRK_ES      SPRT_STAT_BRK0_ES

/*
// Interrupt registers
*/
#define INT_SPRT0	      0xff44	/* sprt 0 interrupt ctrl reg	    */
#define INT_SPRT1	      0xff42	/* sprt 0 interrupt ctrl reg	    */
#define INT_SPRT	      0xff44	/* serial port interrupt control reg*/
#define INT_WDOG_EM	      0xff42	/* Watchdog timer interrupt control */


#define INT_INT4	      0xff40	/* INT4 control register */
#define INT_INT3	      0xff3e	/* INT3 control register */
#define INT_INT2	      0xff3c	/* INT2 control register */
#define INT_INT1	      0xff3a	/* INT1 control register */
#define INT_INT0	      0xff38	/* INT0 control register */

#define INT_DMA1	      0xff36	/* DMA1 interrupt control register */
#define INT_DMA0	      0xff34	/* DMA0 interrupt control register */

#define INT_TMR 	      0xff32	/* Timer interrupt control register */

#define INT_STAT	      0xff30	/* Interrupt status register	*/
#define INT_IREQ	      0xff2e	/* Interrupt request register	*/
#define INT_INSV	      0xff2c	/* In-service register		*/
#define INT_PMSK	      0xff2a	/* Priority mask register	*/
#define INT_MASK	      0xff28	/* Interrupt mask register	*/
#define INT_PSTT	      0xff26	/* Poll status register 	*/
#define INT_POLL	      0xff24	/* Poll register		*/
#define INT_EOI 	      0xff22	/* End-of-interrupt register	*/
#define INT_VEC 	      0xff20	/* Interrupt vector register	*/

/*
// These two fields apply only to INT_INT0 and INT_INT1
*/
#define INT_CASCADE	      0x0020	/*  cascade mode enable      */
#define INT_SFNM	      0x0040	/*  specl fully nested mode  */

/*
// Interrupt Status Register fields (INT_STAT)
*/
#define INT_DHLT	      0x8000	/*  halt DMA activity	     */
#define INT_STAT_TMR2	      0x0004	/*  TMR2 has intrpt pending  */
#define INT_STAT_TMR1	      0x0002	/*  TMR1 has intrpt pending  */
#define INT_STAT_TMR0	      0x0001	/*  TMR0 has intrpt pending  */

/*
// These fields apply to the interrupt request register (INT_IREQ),
// the interrupt in-service register (INT_INSV), and the interrupt
// mask register (INT_MASK)
*/
#define INT_SPT0	      0x0400	 /*  serial port	      */
#define INT_WATCHDOG	      0x0200	 /*  watchdog timer (EM/ER)   */
#define INT_SPT1	      0x0200	 /*  serial port 1 (ES)       */
#define INT_I4		      0x0100	 /*  INT4		      */
#define INT_I3		      0x0080	 /*  INT3		      */
#define INT_I2		      0x0040	 /*  INT2		      */
#define INT_I1		      0x0020	 /*  INT1		      */
#define INT_I0		      0x0010	 /*  INT0		      */
#define INT_D1		      0x0008	 /*  DMA1		      */
#define INT_D0		      0x0004	 /*  DMA0		      */
#define INT_I6		      INT_D1	 /*  DMA1		      */
#define INT_I5		      INT_D0	 /*  DMA0		      */
#define INT_TIMER	      0x0001	 /*  any timer (see INT_STAT) */

/*
// EOI register fields
*/
#define EOI_NONSPEC	      0x8000	 /*  non-specific EOI	      */

/*
// Interrupt poll and poll status register fields
*/
#define INT_POLL_IREQ	      0x8000	 /*  interrupt pending flag   */


/*
// Other serial port bits -- ES Only
*/
#define SPRT_CTL_RSIE_ES      0x1000	  /*  enable Rx status interrupts */
#define SPRT_CTL_BRK_ES       0x0800	  /*  send break		  */
#define SPRT_CTL_TB8_ES       0x0400	  /*  Transmit data bit 8	  */
#define SPRT_CTL_HS_ES	      0x0200	  /*  hardware handshake enable   */
#define SPRT_CTL_TXIE_ES      0x0100	  /*  enable transmit interrupt   */
#define SPRT_CTL_RXIE_ES      0x0080	  /*  enable receive interrupt	  */
#define SPRT_CTL_TMODE_ES     0x0040	  /*  enable transmitter	  */
#define SPRT_CTL_RMODE_ES     0x0020	  /*  enable receiver		  */
#define SPRT_CTL_EVN_ES       0x0010	  /*  even parity		  */
#define SPRT_CTL_PE_ES	      0x0008	  /*  enable parity checking	  */
#define SPRT_CTL_MODE1_ES     0x0001	  /*  Async. mode A		  */
#define SPRT_CTL_MODE2_ES     0x0002	  /*  Async. address recog. mode  */
#define SPRT_CTL_MODE3_ES     0x0003	  /*  Async. mode B		  */
#define SPRT_CTL_MODE4_ES     0x0004	  /*  Async. mode C		  */

/*
// ======================================================================
// Interrupt types
// These are the values to write to the EOI register
*/
#define EOITYPE_TMR0	      0x08
#define EOITYPE_TMR1	      EOITYPE_TMR0
#define EOITYPE_TMR2	      EOITYPE_TMR0
#define EOITYPE_DMA0	      0x0a
#define EOITYPE_DMA1	      0x0b
#define EOITYPE_INT0	      0x0c
#define EOITYPE_INT1	      0x0d
#define EOITYPE_INT2	      0x0e
#define EOITYPE_INT3	      0x0f
#define EOITYPE_INT4	      0x10
#define EOITYPE_INT5	      EOITYPE_DMA0
#define EOITYPE_INT6	      EOITYPE_DMA1
#define EOITYPE_SPRT	      0x14
#define EOITYPE_SPRT0	      0x14
#define EOITYPE_WDOG_EM       0x11	      /* Watchdog timer on EM/ER */
#define EOITYPE_SPRT1	      0x11	      /* Serial port 1 on ES	 */
#define EOITYPE_NONSPEC       0x8000

#define PIO_MODE_0	      0xff70
#define PIO_DIR_0	      0xff72
#define PIO_DATA_0	      0xff74
#define PIO_MODE_1	      0xff76
#define PIO_DIR_1	      0xff78
#define PIO_DATA_1	      0xff7a

#define Com1Base	      0x200
#define Com2Base	      0x100

#define Txbuf		0x00     /* tx buffer */
#define Rxbuf		0x00     /* rx buffer */
#define Dll		0x00     /* baud lsb */
#define Dlh		0x01     /* baud msb */
#define Ier		0x01     /* int enable reg */
#define Fcr		0x02     /* FIFO control register */
#define Iir             0x02     /* Interrupt Identification Register */
#define Lcr		0x03     /* line control reg */
#define Dfr		0x03     /* Data format  reg */
#define Mcr		0x04     /* modem control reg */
#define Lsr		0x05     /* line status reg */

/* ------------------------------------------------------ */

#define IMASK_ON  0x10
#define IMASK_OFF 0x18

#define BUF_SIZE     1024   /* must be 2 ** n */
#define IN_BUF_SIZE  1024
#define OUT_BUF_SIZE  512