i-8080 Specification
Mode | 4 Channel Pulse/Dir Counter
 | 4 Channel Up/Down Counter
 | 8 Channel Frequency
 | 8 Channel Up Counter
Input frequency | 10~450K Hz (Frequency mode) 450K Hz max (Counter mode)
Input Level | Isolated | Logic Level 0 : +1V max
 |  | Logic Level 1 : +4.5V to 30V
 | TTL | Logic Level 0 : 0V to 0.8V
 |  | Logic Level 1 : 2 to 5V
Maximum Pulse Width | 1 µ sec (Frequency mode) 1 µ sec (Counter mode)
Programmable Digital Noise Filter | 1~32767 µ sec
Programmable built-in gate time | 0.33sec (Default)
Power Consumption | 1W
Display | 1 LED as Power/Communication indicator

i-8080 Pin assignments:

i-8080

Isolated Input :

Figure Isolated block diagram

TTL Input:

Figure TTL block diagram

Isolated or TTL input is selected by using JP1 to JP8 as indicated below:

文字方塊:          J1/2/3/4/5/6/7/8         J1/2/3/4/5/6/7/8                            Select isolated input       Select TTL input           (default setting)

J1 | Select A0
J2 | Select B0
J3 | Select A1
J4 | Select B1
J5 | Select A2
J6 | Select B2
J7 | Select A3
J8 | Select B3

The default jumper settings are as follows:

Figure Isolated & TTL Jumper

i-8080 Wiring Connection

Mode0: Dir/Pulse Counter Mode

Mode1: Up/Down Counter Mode

Mode2: Frequency Mode

Mode3: Up Counter Mode

i-8080 Dimension


1

Input signal model

1. Isolated Input (XOR=0)

The operational logic applied on the 8080 modules is the falling edge trigger (Normal High & active Low).
The external signal is input into an 8080 module through the isolated mechanism, with the signal being

reversed from the external signal.
This internal signal is the suggested waveform, as it doesn’t need to execute the XOR operation (XOR=0).

The solution is shown in Figure 1 below.

Figure 1 Isolated input

2. TTL Input (XOR=1)

When an external TTL signal is input into an 8080 module through the TTL mechanism, the signal will be the same as

the external signal. This internal signal isn’t the recommended waveform as it must execute the exclusive OR (XOR=1)

operation. The solution is shown in Figure 2.

3. Always XOR=0

Regardless of whether the input signal is TTL or isolated, XOR is always set to 0, and the maximum count error can

only be 1. XOR=0 can be used for all cases, if a 1-count error is acceptable.

Figure 2 TTL input

Note:

1. When XOR=0 and the 8080 module status is OPEN status ( i.e. no signals on the input terminal) ,

regardless of whether you select the TTL or Isolated mode, the signal at the C point will always be 1.

Similarly, if XOR=1 and the status is OPEN, then the signal at the C point will always be 0.

2. If the input signal is a pulse rather than a 50/50 duty cycle square waveform, then the 1-count error will

not occur as the pulse width is shorter..

Figure 3 Square and pulse waveforms


1

Digital Low Pass Filter

The 8080 has three independent 2nd-order digital noise filters, LP0, LP1 & LP2, to remove noises as follows:

Channel | Low Pass Filter
A0 | Low Pass Filter 0
B0 | Low Pass Filter 0
A1 | Low Pass Filter 1
B1 | Low Pass Filter 1
A2 | Low Pass Filter 2
B2 | Low Pass Filter 2
A3 | Low Pass Filter 2
B3 | Low Pass Filter 2

The Low Pass Filter can be either disabled or programmable from 2 µS to 65535 µS.

The Low Pass Filter will apply to all working modes, counter or frequency.

These 3 Low Pass Filters are disabled status in the default shipping. User defined program can be

used to issue a command to enable or disable the filters.

Assume that the filter clock of the Low Pass Filter is set to T, this clock is used to sample the input signal.

If one of the adjacent 2 samples is low, then the input signal will be removed as follows:

If the high width of the input signal is shorter then T, it will be filtered.

If the adjacent 2 samples are all HIGH, the input signal can pass as indicated below:

Note: the filter signal is shorter than the original input signal.

If the input signal is shorter than 2T, it may be filtered in the following manner:

The relationship between the input signal and the filter signal is as follows:

if (2T<input signal) , it will pass

if (T<=input signal<=2T) , it may be filtered or passed

if (input signal <T) , it will be filtered

The software driver, ‘i8080_SetLowPassUs (int Slot, int Channel, unsigned int Us)’,

provides an parameter, Us which can be used to set the Low Pass Filter as follows:

if Us=1 and 2T =1µS then T = 0.5µS and signal<=0.5µS will be removed

if Us=2 and 2T= 2µS then T = 1 µS and signal<=1µS will be removed

if Us=N, N from 1 to 0x7fff and 2T = N µS then signal<=(N/2) µS will be removed

The Low Pass Filter range can be configured from 1µS to 32767µS. The high width of the signal < (Us/2) will be removed.

For example, if you use a function generator as signal source, the 500Hz signal & 50/50 duty cycle

will generate a 1000µS high & 1000µS low as follows:

Figure 1 Input signal=500Hz & Low Pass Filter Disable

Signal 1 = input signal=500Hz, 50/50 duty cycle

Signal 2 = input signal after Xor and Low Pass Filter, now Xor=0 and Low Pass Filter is disable.

If the Low Pass Filter is disabled, signal 2 will be the same as signal 1 in the above diagram.

If the Low Pass Filter is enabled, signal 2 will be shorter than signal 1 as shown below:

Figure 2 Input signal=500Hz & Low Pass Filter Enable=1µS

Signal 1 = input signal=500Hz, 50/50 duty cycle

Signal 2 = input signal after Xor and Low Pass Filter, now Xor=0 and the Low Pass Filter is enabled.

Nearly all pulses are passed.

Now you can find that nearly all pulses are passed. If the input signal is increased to 600Hz,

then some of the pulses are filtered as follows:

Figure 3 Input signal=600Hz & Low Pass Filter Enabled=1µS

Signal 1 = input signal=600Hz, 50/50 duty cycle.

Signal 2 = input signal after Xor and Low Pass Filter, now Xor =0 and Low Pass Filter is enabled.

Some pulses are filtered.

If the input signal is increased to 900Hz, then nearly all pulses are filtered as illustrated below:

Figure 4 Input signal=900Hz & Low Pass Filter Enabled=1µS

Signal 1 = input signal=900Hz, 50/50 duty cycle

Signal 2 = input signal after Xor and Low Pass Filter, now Xor=0 and the Low Pass Filter is enabled.

Nearly all pulses are filtered.

Because there are some frequency offset errors in the internal crystal, there may be some noises when

the input signal width = Low Pass Filter/2 as follows:

Figure 5 Input signal=1000Hz & Low Pass Filter Enabled=1µS

Signal 1 = input signal=1000Hz, 50/50 duty cycle à pulse width=500 µS

Signal 2 = input signal after Xor and Low Pass Filter, now Xor=0 and the Low Pass Filter is enabled.

Signal Pulse=500 µS=Low Pass Filter/2.

Nearly all pulses are filtered, but sometimes certain noises will not be filtered.

If the input signal is increased to 1100Hz, then all pulses will be filtered as shown in Figure 1-12:

Figure 6 Input signal=1100Hz & Low Pass Filter Enabled=1µS

In summary, apply the minimum 1µS on Low Pass Filters.

The result of the signal being processed by the Low Pass Filter as follows:

Input signal frequency(Hz) | After Low Pass Filter processing | Reference
Input signal <500Hz (Low Pass Filter=1µS) | All signals will be passed | Figure 1
Input signal =500Hz (Low Pass Filter=1µS) | All signals should be passed | Figure 2
Input signal =600Hz (Low Pass Filter=1µS) | Some signals will be filtered and some will be passed | Figure 3
Input signal =900Hz (Low Pass Filter=1µS) | Many signals will be filtered and few will be passed | Figure 4
Input signal =1000Hz (Low Pass Filter=1µS) | Nearly all signals are filtered | Figure 5
Input signal =1100Hz (>1k Hz) (Low Pass Filter=1µS) | All signals will be filtered | Figure 6

For the same reason, if the signal pulse=Low Pass Filter, certain pulses may be filtered. Therefore, it is recommended to set the cycle time of Low Pass Filter about 5% less than the cycle time of input signal pulse as shown below:

Input pulse =1 ms = 1000 µS à set Low Pass Filter <=950 µS

if Input pulse = 100 µS , set Low Pass Filter <= 95 µS

The minimum Low Pass Filter = 1 µS , input signal < 475K, 50/50 duty cycle

As a result, the maximum speed of the 8080 is recommended to 450K, 50/50 duty cycle


Operation Mode

Operation Mode | Description | Number of counter/frequency sets
00 | Dir/Pulse counting mode | 4 sets
01 | Up/Down counting mode | 4 sets
02 | Frequency mode | 8 sets
03 | Up counting mode | 8 sets

The input channels mapping table and working modes are indicated below:

 | Mode 00 | Mode 01 | Mode 02 | Mode 03
A0 | Pulse 0 | Up 0 | Frequency 0 | Up 0
B0 | Dir 0 | Down 0 | Frequency 1 | Up 1
A1 | Pulse 2 | Up 2 | Frequency 2 | Up 2
B1 | Dir 2 | Down 2 | Frequency 3 | Up 3
A2 | Pulse 4 | Up 4 | Frequency 4 | Up 4
B2 | Dir 4 | Down 4 | Frequency 5 | Up 5
A3 | Pulse 6 | Up 6 | Frequency 6 | Up 6
B3 | Dir 6 | Down 6 | Frequency 7 | Up 7

  • CountN = the counter value for channel N, 32bit wide, from -2147483648 to 2147483647

  • OverflowN = the counting overflow number for channel N, 16bit wide, from -32768 to 32767

  • Total Counting Value bit = 32bit + 16bit = 48bit

Mode 00: Pulse /Dir Counting

The counter operation for mode 00 (Dir/Pulse mode) is as follows:

When InB0 is used as Dir, if InB0 is High, counter_0 will be increased by one for every falling edge of InA0.

If InB0 is Low, counter_0 will be decreased by one for every falling edge of InA0.

The counter operation is given as follows:

Pulse/Dir Counter | Counting Variable | Total Counting Value
A0, B0 | Count0, Overflow0 | Count0 + Overflow0 * 2147483648
A1, B1 | Count2, Overflow2 | Count2 + Overflow2 * 2147483648
A2, B2 | Count4, Overflow4 | Count4 + Overflow4 * 2147483648
A3, B3 | Count6, Overflow6 | Count6 + Overflow6 * 2147483648

  • CountN = the counter value for channel N, 32bit wide, from -2147483648 to 2147483647

  • OverflowN = the counting overflow number for channel N, 16bit wide, from -32768 to 32767

  • Total Counting Value bit = 32bit + 16bit = 48bit

Mode 01: Up/Down Counting

The counter operation for mode 01 (Up/Down mode) is as follows:

When InA0 is used as a UP_clock and InB0 is used as a DOWN_clock. The counter_0 will be

increased by one for every falling edge of InA0 and decreased by one for every falling edge of InB0.

Up/Down Counter | Counting Variable | Total Counting Value
A0, B0 | Count0, Overflow0 | Count0 + Overflow0 * 2147483648
A1, B1 | Count2, Overflow2 | Count2 + Overflow2 * 2147483648
A2, B2 | Count4, Overflow4 | Count4 + Overflow4 * 2147483648
A3, B3 | Count6, Overflow6 | Count6 + Overflow6 * 2147483648

  • CountN = the counter value for channel N, 32bit wide, from -2147483648 to 2147483647

  • OverflowN = the counting overflow number for channel N, 16bit wide, from -32768 to 32767

  • Total Counting Value bit = 32bit + 16bit = 48bit

Mode 02: Frequency Mode

The frequency operation for mode 02 is as follows:

Frequency | Frequency Variable
A0 | Frequency0
B0 | Frequency1
A1 | Frequency2
B1 | Frequency3
A2 | Frequency4
B2 | Frequency5
A3 | Frequency6
B3 | Frequency7

Period of update time t =0.33 second is the default setting. A user defined command can be used to

change the value of t for special applications.

Frequency = Counter value / Period of scan time t

Assume t = 0.1 seconds,

If count = 1 à frequency = 1/(0.1/1) = 10 Hz

If count = 10 à frequency = 1/(0.1/10) = 100 Hz

All frequency channels will be updated every 0.1 seconds for t= 0.1 seconds.

The software driver provides three ways to adjust t.

They are Auto select, Low and High Frequency. (The default is Auto select)

The default configuration data is as follows:

Auto Frequency = The frequency channel will be updated every 330 millisecond ;

Low Frequency = The frequency channel will be updated every 1000 millisecond ;

High Frequency = The frequency channel will be updated every 100 millisecond ;

Mode 03: Up Counting

The counter operation for mode 03 is as follows:

Counter_0 will increment by one for every falling edge of InA0

Up Counter | Counting Variable | Total Counting Value
A0 | Count0, Overflow0 | Count0 + Overflow0 * 4294967296
B0 | Count1, Overflow1 | Count1 + Overflow1 * 4294967296
A1 | Count2, Overflow2 | Count2 + Overflow2 * 4294967296
B1 | Count3, Overflow3 | Count3 + Overflow3 * 4294967296
A2 | Count4, Overflow4 | Count4 + Overflow4 * 4294967296
B2 | Count5, Overflow5 | Count5 + Overflow5 * 4294967296
A3 | Count6, Overflow6 | Count6 + Overflow6 * 4294967296
B3 | Count7, Overflow7 | Count7 + Overflow7 * 4294967296

The counter operation is as follows:

  • CountN = current counter value for channel N, 32bit wide, from 0 to 4294967295

  • OverflowN = The counting overflow number for channel N, 16bit wide, from 0 to 65535

  • Total Counting Value = CountN + OverflowN * 4294967296

  • Total Counting Bit = 32bit + 16bit = 48bit


1

EEPROM

The 8080 is equipped with 128bytes (64 words) of EEPROM, allowing the user

to save both system and channel configuration data.

The read/write units for EEPROM are 2bytes, the address 0~31 of EEPROM

is for user design, and address 32~63 is used by 8080 system configuration.

The limitation of EEPROM can be rewrite 1,000,000 times.